This invention is directed to a test set having a new and improved loss of synchronization (sync) detector for testing high speed synchronous data communication channels. In this test set as in the prior art test sets, repeating psuedo random bit patterns are transmitted by a transmitter section and compared with a true replica of the locally generated psuedo random bit pattern.
In this test set however, a novel loss of synchronization detector is provided which allows loss of synchronization to be detected with such rapidity that normal error counting is substantially unaffected. In the prior art test sets, loss of synchronization was determined by monitoring the number of errors in a preset number of received bits and if the number of errors was greater than a predetermined number then it was assumed loss of synchronization occurred.
In the prior art, it was conventional to base a loss of synchronization determination on the detection of about three to six thousand errors. With the present invention it is no longer necessary to count three to six thousand errors to make a determination that loss of synchronization has occurred. With the present invention it is now possible with a high degree of confidence to determine loss of synchronization in as few as 22 bits of received data and even a fewer number of bits e.g., 8 or less if desired, depending upon the number of bits in the psuedo random pattern.
In the preferred embodiment of this invention loss of synchronization is determined if any sixteen errors occur in a row or consecutively, i.e. identical to any sixteen bits of the pseudo random pattern (see FIG. 3), however it should be understood that more than sixteen consecutive errors e.g., 100 errors or less than sixteen consecutive errors may be used for this loss of sync determination depending upon the statistical confidence level that one is willing to accept.
As used herein a bit represents a "1" or "0" digital level e.g., +5v and 0v respectively, as conventionally used in digital systems. This invention provides a further advantage over the prior art in that it is no longer necessary to discard the running error count since loss of synchronization is detected so rapidly.
As used in this disclosure loss of synchronization in a synchronous data transmission system is defined as a slippage of a clock signal, the presence of erronous clock signals, loss of received data or a different frequency in the received data with respect to the clock, all of which leads to a substantial error rate.
Prior art data test sets using the aforementioned prior art loss of synchronization scheme are sold by International Data Systems, Inc. of Providence, R.I. as the Range Rider.RTM. Models 1000, 1100 or 1200 data test sets.